CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06N 3/063 (2013.01); G11C 11/54 (2013.01)] | 19 Claims |
1. A memory for an artificial neural network (ANN) accelerator, comprising:
a first bank including at least two word lines and a plurality of write word selectors, each word line storing a plurality of words, each word having a plurality of bytes, each write word selector having an input port and a plurality of output ports, each write word selector coupled to a corresponding word in each word line, and each write word selector configured to select a byte of the corresponding word of a selected word line based on a byte select signal;
a second bank including at least two word lines and a plurality of write word selectors, each word line storing a plurality of words, each word having a plurality of bytes, each write word selector having an input port and a plurality of output ports, each write word selector coupled to a corresponding word in each word line, and each write word selector configured to select a byte of the corresponding word of a selected word line based on the byte select signal; and
a bank selector, coupled to the inputs of the write word selectors of the first bank and the inputs of the write word selectors of the second bank, configured to select a combination of write word selectors from at least one of the first bank and the second bank based on a bank select signal,
where:
the write word selectors are column multiplexers and the byte select signal is a column multiplexer select signal; and
the bank selector is a bank multiplexer and the bank select signal is a bank multiplexer select signal.
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