US 12,086,449 B1
Repair operation techniques
Alan J. Wilson, Boise, ID (US); and Donald M. Morgan, Meridan, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 8, 2022, as Appl. No. 17/983,213.
Application 17/983,213 is a continuation of application No. 17/197,733, filed on Mar. 10, 2021, granted, now 11,507,296.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/10 (2016.01)
CPC G06F 3/0647 (2013.01) [G06F 3/0616 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/10 (2013.01); G06F 2212/657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
determining a failure of a read operation associated with a physical row address of a memory device;
storing, after determining the failure and before performing a wear leveling operation, information associated with the physical row address based at least in part on determining the failure; and
performing a repair operation on the physical row address based at least in part on the stored information associated with the physical row address.