US 12,086,447 B2
Systems and methods for reducing instruction code memory footprint for multiple processes executed at a coprocessor
Khaled Hamidouche, Austin, TX (US); Michael W. Lebeane, Austin, TX (US); and Hari S. Thangirala, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Dec. 18, 2019, as Appl. No. 16/719,076.
Prior Publication US 2021/0191641 A1, Jun. 24, 2021
Int. Cl. G06F 3/06 (2006.01); G06F 12/0882 (2016.01)
CPC G06F 3/0647 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G06F 12/0882 (2013.01); G06F 2212/7201 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a page migration trigger for a page present in a first memory associated with a first processor; and
responsive to the page migration trigger:
when the page is a read-only page storing code for execution:
migrating the page to a code cache portion of a second memory associated with a second processor and shared by multiple processes executing at the second processor;
configuring each process of a set of processes executing at the second processor to access and execute the code from the code cache portion; and
creating a read-only mapping in a virtual address space of a first process of the multiple processes, wherein the read-only mapping occurs after text relocations in the read-only page; and
when the page is a non-read-only page not storing code for execution, migrating the page to a non-code cache portion of the second memory.