US 12,086,446 B2
Memory and storage pool interfaces
Sujoy Sen, Beaverton, OR (US); Thomas E. Willis, Redwood City, CA (US); Durgesh Srivastava, Cupertino, CA (US); Marcelo Cintra, Braunschweig (DE); Bassam N. Coury, Portland, OR (US); Donald L. Faw, Hillsboro, OR (US); and Francois Dugast, Karlsruhe (DE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2020, as Appl. No. 17/031,721.
Claims priority of provisional application 62/924,121, filed on Oct. 21, 2019.
Prior Publication US 2021/0019069 A1, Jan. 21, 2021
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0644 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/067 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method comprising:
translating, at an interface, a first input format message for a first memory access request to a format accepted by a memory controller for a media of a disaggregated memory pool, wherein the interface comprises a network interface and the first memory access request is associated with one or more Ethernet packets received by the network interface and the disaggregated memory pool comprises a plurality of volatile memory devices accessible through a network;
providing the translated first input format message to the memory controller;
providing, at the memory controller, the translated first memory access request in the format accepted by the media of the disaggregated memory pool;
translating, at the interface, a second input format message for a second memory access request to the format accepted by the memory controller, wherein the second memory access request is in a Compute Express Link (CXL) format;
providing the translated second input format message to the memory controller; and
providing, at the memory controller, the translated second memory access request in the format accepted by the media of the disaggregated memory pool.