US 12,086,439 B2
Memory storage with selected performance mode
Shunichi Igahara, Kamakura (JP); Toshikatsu Hida, Yokohama (JP); Riki Suzuki, Yokohama (JP); Takehiko Amaki, Yokohama (JP); Suguru Nishikawa, Osaka (JP); and Yoshihisa Kojima, Kawasaki (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jun. 29, 2023, as Appl. No. 18/343,835.
Application 18/343,835 is a continuation of application No. 17/028,087, filed on Sep. 22, 2020, granted, now 11,733,888.
Application 17/028,087 is a continuation of application No. 16/117,262, filed on Aug. 30, 2018, granted, now 10,824,353, issued on Nov. 3, 2020.
Claims priority of application No. 2017-182025 (JP), filed on Sep. 22, 2017.
Prior Publication US 2023/0342051 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/10 (2016.01)
CPC G06F 3/0634 (2013.01) [G06F 3/0604 (2013.01); G06F 3/061 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0253 (2013.01); G06F 12/10 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A controller for a memory system connectable to a host, the memory system including a nonvolatile memory, the nonvolatile memory including a plurality of memory cells, the controller comprising:
an interface circuit configured to communicate with the host; and
a first circuit configured to write data to the nonvolatile memory in either a first mode or a second mode, a number of bits of data written in a memory cell in the second mode being larger than a number of bits of data written in a memory cell in the first mode, wherein
the first circuit is further configured to:
determine a size of a first region of the nonvolatile memory for writing data in the first mode, based on a ratio of (A) a total number of logical addresses mapped to physical addresses of the nonvolatile memory to (B) an entire logical address space of the memory system;
write first data, which is received from the host, into the first region in the first mode;
upon a size of an available area in the first region being smaller than a first threshold, determine to write the first data stored in the first region into a second region of the nonvolatile memory in the second mode; and
write the first data stored in the first region into the second region of the nonvolatile memory in the second mode.