US 12,086,428 B2
Memory controller adjusting power, memory system including same, and operating method for memory system
Hyunseok Kim, Seoul (KR); Jingyu Heo, Yongin-si (KR); Inhae Kang, Seongnam-si (KR); and Jaeyoul Oh, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 13, 2022, as Appl. No. 17/839,388.
Claims priority of application No. 10-2021-0157081 (KR), filed on Nov. 15, 2021; and application No. 10-2021-0185404 (KR), filed on Dec. 22, 2021.
Prior Publication US 2023/0152989 A1, May 18, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 13/00 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An operating method for a memory system, the operating method comprising:
transmitting, to a host via a host interface, maximum power information and step information;
receiving, from the host via the host interface, power table information and battery information in response to the maximum power information and the step information; and
controlling power consumption by a component of the memory system in response to a maximum consumption power value of the memory system,
wherein the power table information is related to a battery associated with the memory system and configured to operate in accordance with a plurality of battery steps,
wherein the power table information includes a number of entries including a first entry and a second entry,
wherein the first entry comprises a first battery step among the plurality of battery steps and is associated with a first maximum consumption power value that comprises a difference between the maximum power consumption value of the memory system and a first maximum power offset corresponding to the first battery step, and
wherein the second entry comprises a second battery step among the plurality of battery steps and is associated with a second maximum consumption power value that comprises a difference between the maximum power consumption value of the memory system and a second maximum power offset corresponding to the second battery step, and
wherein the maximum consumption power value used to control power consumption by the component of the memory system is one of the first maximum consumption power value and the second maximum consumption power value.