US 12,086,426 B2
Memory system, information processing system, and host device
Takahiro Kurita, Sagamihara Kanagawa (JP); Shinichi Kanno, Ota Tokyo (JP); and Yuki Sasaki, Kamakura Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 25, 2021, as Appl. No. 17/412,028.
Claims priority of application No. 2021-047518 (JP), filed on Mar. 22, 2021.
Prior Publication US 2022/0300172 A1, Sep. 22, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile memory; and
a controller configured to:
control the nonvolatile memory to reduce an amount of power consumption of the memory system based on a first instruction received from a host device connected to the memory system;
execute a first process and a second process; and
reduce a processing amount of the second process based on the first instruction;
wherein the first process includes transferring data between the host device and the nonvolatile memory, and the second process includes transcribing data in the nonvolatile memory;
wherein the controller is further configured to:
receive a first value relating to a power consumption and a second value relating to a time period from the host device;
manage an accumulated amount of the power consumption of the memory system consumed since a first timing; and
control the power consumption of the memory system so that the accumulated amount of the power consumption from the first timing to a second timing does not exceed an amount corresponding to the first value, wherein a length from the first timing to the second timing corresponds to the second value,
wherein the nonvolatile memory includes a plurality of memory cell transistors, and
the controller is configured to reduce the amount of the power consumption by reducing the number of bits of data to be written in one of the memory cell transistors configured as a write destination,
wherein the plurality of memory cell transistors are divided into a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation, and
the controller is configured to write data with a first number of bits in the memory cell transistor of the write destination when the number of free blocks among the plurality of blocks is smaller than a third value, and write data with a second number of bits in the memory cell transistor of the write destination when the number of free blocks among the plurality of blocks is larger than the third value, the second number being smaller than the first number.