US 12,086,418 B1
Memory sprinting
Vignesh Adhinarayanan, Austin, TX (US); Michael Ignatowski, Austin, TX (US); and Hyung-Dong Lee, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Mar. 31, 2023, as Appl. No. 18/129,436.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0634 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory controller for selecting memory access commands for dispatch over a memory channel to a dynamic random access memory (DRAM); and
a memory sprint controller in communication with the memory controller that, responsive to an indicator of an irregular memory access phase, causes the memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of the DRAM to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.