US 12,086,412 B2
Balancing performance between interface ports in a memory sub-system
Raja V. S. Halaharivi, Gilroy, CA (US); and Prateek Sharma, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 31, 2022, as Appl. No. 17/900,120.
Prior Publication US 2024/0069732 A1, Feb. 29, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device;
a first interface port and a second interface port operatively coupled with the memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
detecting a triggering event associated with the first interface port;
responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device;
receiving, from the firmware component, a configuration setting based on the interrupt message, wherein the configuration setting comprises one or more instructions referencing (i) an arbitration method for allocating one or more resources to the first interface port and (ii) a threshold period of time for using the arbitration method;
identifying the arbitration method and the threshold period of time referenced in the one or more instructions of the configuration setting; and
allocating, by the processing device, the one or more resources to the first interface port according to the identified arbitration method for the threshold period of time;
wherein the one or more resources include memory access commands.