US 12,086,094 B2
Apparatus and method for communication on a serial bus
Arnaud Dehamel, Monestier de Clermon (FR)
Assigned to STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed on Sep. 4, 2020, as Appl. No. 17/012,984.
Claims priority of application No. 1909970 (FR), filed on Sep. 10, 2019.
Prior Publication US 2021/0073168 A1, Mar. 11, 2021
Int. Cl. G06F 13/42 (2006.01); G06F 1/3237 (2019.01); G06F 9/4401 (2018.01); G06F 9/54 (2006.01); G06F 11/30 (2006.01)
CPC G06F 13/4295 (2013.01) [G06F 1/3237 (2013.01); G06F 9/4418 (2013.01); G06F 9/546 (2013.01); G06F 11/3027 (2013.01); G06F 13/4291 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of communication via a serial bus, the method comprising:
receiving, by a circuit coupled to the serial bus, a frame having a data portion comprising at least two consecutive cycles, each cycle having a dominant state followed by a recessive state, and the recessive states and the dominant states having durations of between 2 and 5 times a data bit-duration of a data bit conveyed by the serial bus;
triggering a starting of a clock signal in the circuit based on an edge of the frame beginning a previous dominant state preceding the dominant states;
detecting, by the circuit using the clock signal, at least one cycle of the at least two consecutive cycles of the frame, the clock signal providing consecutive clock cycles to the circuit for a full duration of the at least one cycle of the at least two consecutive cycles of the frame, and the consecutive clock cycles starting after a beginning of the at least two consecutive cycles of the frame such the circuit does not recognize an initial part of the of the at least two consecutive cycles of the frame; and
triggering, in response to the detecting, a transition from a sleep state to a wake state of the circuit.