US 12,086,082 B2
PASID based routing extension for scalable IOV systems
Pratik Marolia, Hillsboro, OR (US); Sanjay Kumar, Hillsboro, OR (US); Rajesh Sankaran, Portland, OR (US); and Utkarsh Y. Kakaiya, Folson, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 21, 2020, as Appl. No. 17/026,516.
Prior Publication US 2021/0004338 A1, Jan. 7, 2021
Int. Cl. G06F 13/20 (2006.01); G06F 3/06 (2006.01); G06F 9/455 (2018.01)
CPC G06F 13/20 (2013.01) [G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0662 (2013.01); G06F 3/0679 (2013.01); G06F 9/45558 (2013.01)] 21 Claims
OG exemplary drawing
 
16. A system, comprising:
a host central processing unit (CPU) having a plurality of cores, a memory controller, and an input-output memory management unit (IOMMU);
host memory, coupled to the memory controller on the host CPU;
an accelerator, coupled to the CPU and having local memory embedded thereon or coupled to local memory;
an Input/Output Virtualization (IOV) device, operatively coupled to the accelerator and the host CPU and including an Assignable Device Interface (ADI) implementing a Control Process Address Space Identifier (C-PASID) associated with a first memory space in the host memory and a Data PASID (D-PASID) associated with a second memory space in the local memory of the accelerator;
wherein the system is configured to,
use the C-PASID to fetch a descriptor in the first memory space; and
use the D-PASID to fetch data in the second memory space.