US 12,086,080 B2
Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits
George Chrysos, Portland, OR (US); Bhargavi Narayanasetty, Portland, OR (US); Jesus Corbal, King City, OR (US); Ching-Kai Liang, Hillsboro, OR (US); Chinmay Ashok, Beaverton, OR (US); and Francis Tseng, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2020, as Appl. No. 17/033,728.
Prior Publication US 2022/0100680 A1, Mar. 31, 2022
Int. Cl. G06F 13/16 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 13/4027 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory;
a hardware processor core to execute one or more instructions to offload dataflow operations, the hardware processor core coupled to the memory; and
a dataflow driven accelerator, to perform the dataflow operations, coupled to the hardware processor core, wherein the dataflow driven accelerator comprises:
at least one dataflow execution circuit that each comprises:
a register file,
a plurality of execution circuits, and
a graph station circuit comprising a plurality of dataflow operation entries that each include a respective ready field that indicates when an input operand for a dataflow operation is available in the register file, and the graph station circuit is to select for execution a first dataflow operation entry when its input operands are available, and clear ready fields of the input operands in the first dataflow operation entry when a result of the execution is stored in the register file, and
a memory execution interface coupled between the at least one dataflow execution circuit and the memory to send data between the at least one dataflow execution circuit and the memory according to a second dataflow operation entry.