US 12,086,078 B2
Memory chip having an integrated data mover
Samuel E. Bradshaw, Sacramento, CA (US); Shivam Swami, Folsom, CA (US); Sean Stephen Eilert, Penryn, CA (US); Justin M. Eno, El Dorado Hills, CA (US); and Ameen D. Akel, Rancho Cordova, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 15, 2022, as Appl. No. 17/888,392.
Application 17/888,392 is a continuation of application No. 16/573,780, filed on Sep. 17, 2019, granted, now 11,416,422.
Prior Publication US 2022/0391330 A1, Dec. 8, 2022
Int. Cl. G06F 12/0802 (2016.01); G06F 3/06 (2006.01); G06F 13/00 (2006.01); G06F 13/10 (2006.01); G06F 13/12 (2006.01)
CPC G06F 13/102 (2013.01) [G06F 3/06 (2013.01); G06F 12/0802 (2013.01); G06F 13/124 (2013.01); G06F 2212/621 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first memory device of a string of memory devices comprising:
a first set of pins configured to couple the first memory device to a device having a device set of pins, wherein the device comprises a memory controller or processor, and wherein the first set of pins are directly connected via wiring to the device set of pins; and
a second set of pins configured to couple the first memory device to a second memory device of the string of memory devices; and
the second memory device comprising:
a third set of pins configured to couple the second memory device to the first memory device; and
a fourth set of pins configured to couple the second memory device to a third memory device,
wherein, to read data from or write data to the second memory device or the third memory device, the device is configured to communicate with the first memory device and not either of the second memory device or the third memory device.