US 12,086,074 B2
Method and apparatus for permuting streamed data elements
Soujanya Narnur, Austin, TX (US); Timothy David Anderson, University Park, TX (US); Mujibur Rahman, Plano, TX (US); and Duc Quang Bui, Grand Prairie, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 22, 2023, as Appl. No. 18/321,050.
Application 18/321,050 is a continuation of application No. 17/588,416, filed on Jan. 31, 2022, granted, now 11,669,463.
Application 17/588,416 is a continuation of application No. 16/878,611, filed on May 20, 2020, granted, now 11,237,831, issued on Feb. 1, 2022.
Claims priority of provisional application 62/852,870, filed on May 24, 2019.
Prior Publication US 2023/0289296 A1, Sep. 14, 2023
Int. Cl. G06F 12/10 (2016.01); G06F 7/24 (2006.01); G06F 7/487 (2006.01); G06F 7/499 (2006.01); G06F 7/53 (2006.01); G06F 7/57 (2006.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 12/0862 (2016.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 12/1009 (2016.01); G06F 12/1045 (2016.01); G06F 17/16 (2006.01); H03H 17/06 (2006.01); G06F 15/78 (2006.01)
CPC G06F 12/1045 (2013.01) [G06F 7/24 (2013.01); G06F 7/487 (2013.01); G06F 7/4876 (2013.01); G06F 7/49915 (2013.01); G06F 7/53 (2013.01); G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/30021 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30065 (2013.01); G06F 9/30072 (2013.01); G06F 9/30098 (2013.01); G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/3016 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/383 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3856 (2023.08); G06F 9/3867 (2013.01); G06F 9/3887 (2013.01); G06F 9/48 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 17/16 (2013.01); H03H 17/0664 (2013.01); G06F 9/30018 (2013.01); G06F 9/325 (2013.01); G06F 9/381 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 15/7807 (2013.01); G06F 15/781 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/602 (2013.01); G06F 2212/68 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a cache controller interface configured to receive a set of data elements, wherein the cache controller interface includes:
a buffer configured to store the set of data elements;
a first circuit coupled to the buffer and configured to reorder bits of the set of data elements according to a first finite impulse response operation to produce the set of data elements in a first arrangement;
a second circuit coupled to the buffer in parallel with the first circuit and configured to reorder the bits of the set of data elements according to a second finite impulse response operation to produce the set of data elements in a second arrangement that is different from the first arrangement; and
a selection circuit coupled to the first circuit and the second circuit and configured to select between providing the set of data elements in the first arrangement or the set of data elements in the second arrangement; and
a processor functional unit coupled to the selection circuit and configured to selectably perform either the first finite impulse response operation or the second finite impulse response operation on the set of data elements.