US 12,086,070 B2
Block device interface using non-volatile pinned memory
Stuart John Inglis, Cambridge (NZ); Timothy Kelly Dawson, Cambridge (NZ); Xavier Aldren Simmons, Cambridge (NZ); Sheridan John Lambert, Cambridge (NZ); Rafael John Patrick Shuker, Cambridge (NZ); Dominic Joseph Michael Houston Azaris, Cambridge (NZ); and Alexander Kingsley St. John, Cambridge (NZ)
Assigned to DAEDALUS CLOUD LLC, Croton-on-Hudson, NY (US)
Filed by Daedalus Cloud LLC, Croton-on-Hudson, NY (US)
Filed on Jan. 19, 2022, as Appl. No. 17/579,264.
Application 17/579,264 is a continuation of application No. 16/556,575, filed on Aug. 30, 2019, granted, now 11,263,144.
Claims priority of provisional application 62/746,981, filed on Oct. 17, 2018.
Claims priority of provisional application 62/725,703, filed on Aug. 31, 2018.
Claims priority of provisional application 62/725,691, filed on Aug. 31, 2018.
Prior Publication US 2022/0138111 A1, May 5, 2022
Int. Cl. G06F 12/10 (2016.01); G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G06F 12/0815 (2016.01); G06F 12/12 (2016.01); G06F 12/14 (2006.01)
CPC G06F 12/10 (2013.01) [G06F 3/0607 (2013.01); G06F 3/065 (2013.01); G06F 9/30036 (2013.01); G06F 9/30123 (2013.01); G06F 9/3877 (2013.01); G06F 11/1004 (2013.01); G06F 11/1088 (2013.01); G06F 12/0246 (2013.01); G06F 12/0815 (2013.01); G06F 12/12 (2013.01); G06F 12/1408 (2013.01); G06F 3/0679 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/657 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, at a block device interface, an instruction to write data, the instruction comprising a memory location of the data;
copying the data to pinned memory;
indicating to a sender of the instruction that the data in the pinned memory has been written to one or more storage devices before performing one or more invertible transforms on the data;
performing, by a vector processor, the one or more invertible transforms on the data to generate transformed data;
writing the transformed data to the pinned memory; and
initiating a transfer of the transformed data from the pinned memory to the one or more storage devices in response to a block device driver determining that the transformed data must be moved from the pinned memory to the one or more storage devices,
wherein contents of the pinned memory are accessible by the vector processor and a central processing unit (CPU) directly over a data bus.