US 12,086,067 B2
Load-store pipeline selection for vectors
Andrew Waterman, Berkeley, CA (US); and Krste Asanovic, Oakland, CA (US)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on Apr. 30, 2023, as Appl. No. 18/141,463.
Claims priority of provisional application 63/341,051, filed on May 12, 2022.
Prior Publication US 2023/0367715 A1, Nov. 16, 2023
Int. Cl. G06F 12/0855 (2016.01); G06F 12/0815 (2016.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01)
CPC G06F 12/0855 (2013.01) [G06F 12/0815 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a processor core configured to execute vector instructions that operate on vector arguments;
an L1 cache that provides an interface to a memory system of the integrated circuit;
an L2 cache connected to the L1 cache that implements a cache coherency protocol with the L1 cache;
a first store unit configured to write data to the memory system via the L1 cache;
a second store unit configured to bypass the L1 cache and write data to the memory system via the L2 cache; and
a store pipeline selection circuitry configured to:
identify an address associated with a first beat of a store instruction with a vector argument;
select between the first store unit and the second store unit based on the address associated with the first beat of the store instruction; and
dispatch the store instruction to the selected store unit.