US 12,086,066 B1
Cache architecture for a massively parallel processing array
Martin Alan Franz, II, Dallas, TX (US)
Assigned to Cornami, Inc., Dallas, TX (US)
Filed by Cornami, Inc., Dallas, TX (US)
Filed on Mar. 15, 2023, as Appl. No. 18/184,536.
Int. Cl. G06F 12/0813 (2016.01)
CPC G06F 12/0813 (2013.01) [G06F 2212/1041 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A cache architecture for an array of identical cores arranged in a grid, each of the cores including interconnections to neighboring cores in the grid, a memory, and an algorithmic logic unit, the cache architecture comprising:
a first core of the array configured to receive a memory access request for data from at least one core of the array of cores configured to perform a computational operation;
a second core of the array configured to determine whether the requested data is present in a cache memory via a cache index including addresses in the cache memory; and
a third core of the array configured as the cache memory, wherein the memory of the third core is used as the cache memory, wherein an address of the requested data from the cache index is passed to the third core to output the requested data.