US 12,086,065 B2
Computing system with direct invalidation in a hierarchical cache structure based on at least one designated key identification code
Weilin Wang, Beijing (CN); Yingbing Guan, Shanghai (CN); and Lei Yi, Xi'an (CN)
Assigned to SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD., Shanghai (CN)
Filed by Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai (CN)
Filed on Oct. 14, 2022, as Appl. No. 18/046,625.
Claims priority of application No. 202111375184.6 (CN), filed on Nov. 19, 2021.
Prior Publication US 2023/0161704 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0811 (2016.01); G06F 12/0808 (2016.01); G06F 12/0831 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 12/0808 (2013.01); G06F 12/0831 (2013.01)] 31 Claims
OG exemplary drawing
 
1. A computing system with direct invalidation in a hierarchical cache structure based on one single designated key identification code, comprising:
a first core provided by a first processor that is fabricated on a first die, including a decoder, a memory ordering buffer, and a first in-core cache module; and
a first last-level cache, fabricated in the first processor;
wherein:
in response to a first instruction of an instruction set architecture that is provided for direct invalidation in a hierarchical cache structure based on one single designated key identification code, the decoder outputs at least one microinstruction, wherein the direct invalidation is performed without writing back;
based on the at least one microinstruction, a direct invalidation request is provided to the first in-core cache module through the memory ordering buffer, and then passed to the first last-level cache by the first in-core cache module;
in response to the direct invalidation request, the first last-level cache searches itself to determine which cache lines within the first last-level cache match the designated key identification code, and invalidates all matched cache lines within the first last-level cache, without writing back the matched cache lines from the first last-level cache to a system memory; and
a first storage unit, storing the designated key identification code indicated by the first instruction;
wherein:
the direct invalidation request does not carry the designated key identification code;
in response to the direct invalidation request, the first last-level cache obtains the designated key identification code from the first storage unit, and searches itself according to the designated key identification code obtained from the first storage unit to determine which cache lines within the first last-level cache match the designated key identification code.