US 12,086,064 B2
Aliased mode for cache controller
Abhijeet Ashok Chachad, Plano, TX (US); Timothy David Anderson, University City, TX (US); Pramod Kumar Swami, Bangalore (IN); Naveen Bhoria, Plano, TX (US); David Matthew Thompson, Dallas, TX (US); and Neelima Muralidharan, Murphy, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 22, 2022, as Appl. No. 17/847,131.
Application 17/847,131 is a continuation of application No. 16/882,344, filed on May 22, 2020, granted, now 11,392,498.
Claims priority of provisional application 62/852,461, filed on May 24, 2019.
Prior Publication US 2022/0327055 A1, Oct. 13, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/10 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 12/10 (2013.01); G06F 2212/608 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory including a first portion and a second portion;
a memory switch control register;
a memory map control register; and
a memory controller coupled to the memory, the memory map control register, and the memory switch control register, wherein the memory controller is configured to:
receive a first memory access instruction associated with a virtual address associated with the first portion;
receive a second memory access instruction associated with the virtual address; and
in response to the memory map control register indicating an aliased mode and the memory switch control register indicating a first value:
direct the first memory access instruction to a first physical address in the first portion of the memory; and
direct the second memory access instruction to a second physical address in the second portion of the memory.