US 12,086,060 B2
Interconnect based address mapping for improved reliability
Taeksang Song, San Jose, CA (US); Steven C. Woo, Saratoga, CA (US); and Torsten Partsch, San Jose, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Aug. 23, 2022, as Appl. No. 17/893,790.
Claims priority of provisional application 63/329,707, filed on Apr. 11, 2022.
Claims priority of provisional application 63/241,304, filed on Sep. 7, 2021.
Prior Publication US 2023/0081231 A1, Mar. 16, 2023
Int. Cl. G06F 12/06 (2006.01); G11C 11/408 (2006.01)
CPC G06F 12/06 (2013.01) [G11C 11/4087 (2013.01); G06F 2212/1032 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory module, comprising:
a module command/address interface to receive a first row address;
a first memory device including a first memory array and a first device command/address interface, the first memory device to receive, via the first device command/address interface, a second row address generated from the first row address using a first mapping that comprises a first permutation function relating signals received via the module command/address interface to signals provided to the first device command/address interface, the second row address to access a first row in the first memory array having a first internal row address, the first row to be physically next to a first neighboring row having a first internal neighboring row address, the first memory device including circuitry to, when in a first operating mode, translate the second row address to the first row address; and
a second memory device including a second memory array and a second device command/address interface, the second memory device to receive, via the second device command/address interface, a third row address generated from the first row address using a second mapping that comprises a second permutation function relating signals received via the module command/address interface to signals provided to the second device command/address interface, the third row address to access a second row in the second memory array having a second internal neighboring row address, the second row to be physically next to a second neighboring row having a second internal neighboring row address, wherein the first internal neighboring row address and the second internal neighboring row address do not address a same row.