US 12,086,026 B2
Multiple error correction code (ECC) engines and ECC schemes
Keun Soo Song, Boise, ID (US); Kang-Yong Kim, Boise, ID (US); and Hyun Yoo Lee, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 10, 2022, as Appl. No. 17/654,354.
Claims priority of provisional application 63/162,139, filed on Mar. 17, 2021.
Prior Publication US 2022/0300370 A1, Sep. 22, 2022
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1044 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0629 (2013.01); G06F 3/0673 (2013.01)] 52 Claims
OG exemplary drawing
 
42. A method comprising:
transmitting a first write command and a first error correction code (ECC) value to a memory module, the first ECC value having a first quantity of bits;
transmitting a command to disable a masked-write functionality of the memory module; and
transmitting a second write command and a second ECC value to the memory module, the second ECC value having a second quantity of bits, the second quantity of bits larger than the first quantity of bits responsive to the command to disable the masked-write functionality of the memory module.