| CPC G06F 1/3275 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01)] | 20 Claims |
|
1. An electronic device, comprising:
a semiconductor memory device configured to store process information and to output the process information to outside of the semiconductor memory device, the process information being programmed in the semiconductor memory device as a part of a process of manufacturing the semiconductor memory device and indicating whether the process used to manufacture the semiconductor memory device is a legacy process or an enhanced process which provides higher device performance than the legacy process; and
a host configured to read the process information from the semiconductor memory device, to select a target operation mode from among a plurality of operation modes depending on the process information, and to set an operation mode of the semiconductor memory device based on the selected target operation mode,
wherein:
the plurality of operation modes define a plurality of respectively different latencies, by which data are output from the semiconductor memory device in response to a read command,
the plurality of respectively different latencies include a first latency and a second latency, the second latency being longer than the first latency, and
the host is further configured to select, from among the plurality of operation modes, a first operation mode corresponding to the first latency in response to the process information indicating the enhanced process as the target operation mode, and to select, from among the plurality of operation modes, a second operation mode corresponding to the second latency in response to the process information indicating the legacy process as the target operation mode.
|