US 12,085,815 B2
Substrate module, display apparatus, and liquid crystal antenna
Zhenyu Jia, Shanghai (CN); Kerui Xi, Shanghai (CN); Ping Su, Shanghai (CN); Baiquan Lin, Shanghai (CN); Linzhi Wang, Shanghai (CN); Qingsan Zhu, Shanghai (CN); Xiaonan Han, Shanghai (CN); Yifan Xing, Shanghai (CN); Xin Li, Shanghai (CN); and Feng Qin, Shanghai (CN)
Assigned to Shanghai Tianma Micro-Electronics Co., Ltd., Shanghai (CN)
Filed by Shanghai Tianma Micro-Electronics Co., Ltd., Shanghai (CN)
Filed on Aug. 4, 2022, as Appl. No. 17/880,994.
Claims priority of application No. 202210621782.5 (CN), filed on Jun. 1, 2022.
Prior Publication US 2023/0393437 A1, Dec. 7, 2023
Int. Cl. G02F 1/1345 (2006.01); H01Q 1/38 (2006.01); H01Q 3/36 (2006.01); G06F 1/16 (2006.01)
CPC G02F 1/1345 (2013.01) [H01Q 1/38 (2013.01); H01Q 3/36 (2013.01); G06F 1/1698 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A substrate module, comprising:
a first substrate, wherein the first substrate includes a first sub-region and a second sub-region; the second sub-region is on a side of the first sub-region along a first direction; the second sub-region includes a binding region; the binding region includes a plurality of first pins arranged along a second direction; and the first direction intersects the second direction, wherein:
the plurality of first pins includes at least one first sub-pin and at least one second sub-pin;
the first sub-region includes a plurality of first loads, and a first sub-pin is electrically connected to a first load of the plurality of first loads;
the second sub-region includes at least one second load, and a second sub-pin is electrically connected to a second load;
the second load includes a capacitor including a first capacitor;
the first substrate includes a first base substrate, and further includes a first electrode layer, a first insulating layer and a second electrode layer which are sequentially arranged on a side of the first base substrate;
the first electrode layer includes a first electrode portion; the second electrode layer includes a second electrode portion; and the second electrode portion is electrically connected to the second sub-pin;
along a direction perpendicular to a plane of the base substrate, the first electrode portion is at least partially overlapped with the second electrode portion; and an overlapping portion of the first electrode portion and the second electrode portion forms the first capacitor;
a first pin of the plurality of first pins includes a first sub-portion and a second sub-portion which are electrically connected with each other; the first sub-portion is in the second electrode layer; and the second sub-portion is in the first electrode layer;
the plurality of first pins further includes at least one third sub-pin, and the first electrode portion is electrically connected to a third sub-pin;
each of a second sub-portion of the first sub-pin and a second sub-portion of the second sub-pin is insulated from the first electrode portion in the first electrode layer; and
a second sub-portion of the third sub-pin is electrically connected to the first electrode portion.