US 12,085,612 B2
On-chip debugging device and method
Fushan Jia, Suzhou (CN); Rui Jiang, Suzhou (CN); and Jicun Zhang, Suzhou (CN)
Assigned to Suzhou Centec Communications Co., Ltd., Suzhou (CN)
Appl. No. 17/594,034
Filed by Suzhou Centec Communications Co., Ltd., Suzhou (CN)
PCT Filed Dec. 2, 2019, PCT No. PCT/CN2019/122393
§ 371(c)(1), (2) Date Apr. 20, 2022,
PCT Pub. No. WO2020/207040, PCT Pub. Date Oct. 15, 2020.
Claims priority of application No. 201910288054.5 (CN), filed on Apr. 11, 2019.
Prior Publication US 2022/0252665 A1, Aug. 11, 2022
Int. Cl. G06F 11/00 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01); G06F 11/22 (2006.01); G06F 11/30 (2006.01)
CPC G01R 31/3187 (2013.01) [G01R 31/318597 (2013.01); G06F 11/221 (2013.01); G06F 11/2289 (2013.01); G06F 11/3089 (2013.01)] 2 Claims
OG exemplary drawing
 
1. An on-chip debugging method, comprising the steps of:
determining a sampling type and a debugging trigger condition according to a configuration of an external debugger or a chip to be debugged;
starting a debugging operation, sampling and recording an internal signal of the chip of a specified type, and further identifying a running state of the chip;
monitoring each trigger condition in a debugging process, and executing corresponding adjustment and debugging after the trigger condition is met; and
modifying a running mode of the chip according to a debugging configuration of the external debugger or an internal CPU (Central Processing Unit) when a preset situation occurs in a chip running process;
wherein the preset situation comprises an error occurring in the chip running process; and
wherein the step of modifying the running mode of the chip comprises: pausing an operation of a chip functional module so as to keep the running state when an error occurs, and outputting, by an internal bus interface, a control signal for pausing the operation of a corresponding functional module;
wherein the trigger condition comprises a chip running state error;
wherein the adjustment and debugging comprises stopping sampling the chip running state information immediately or after waiting for preset time, and marking current sampled running state information as last running state information by a preset identifier when the chip running state information is written into an internal debugging memory.