US 12,085,602 B2
Test circuit monitoring PBTI and operating method thereof
Min Cheol Kim, Icheon-si (KR); Mi Ran Kim, Icheon-si (KR); and Chang Hwi Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 12, 2022, as Appl. No. 18/079,489.
Claims priority of application No. 10-2022-0079919 (KR), filed on Jun. 29, 2022.
Prior Publication US 2024/0003961 A1, Jan. 4, 2024
Int. Cl. G01R 31/26 (2020.01)
CPC G01R 31/2642 (2013.01) [G01R 31/2628 (2013.01)] 15 Claims
OG exemplary drawing
 
11. A method of operating a test circuit, the method comprising:
providing a device including the test circuit, wherein the test circuit includes: a positive bias temperature instability (PBTI) monitoring unit driven according to a power voltage, the PBTI monitoring unit outputting an output voltage having a potential that is equal to or lower than a potential of the power voltage according to a PBTI degradation rate of an NMOS transistor; and a degradation determiner configured to determine the PBTI degradation rate by comparing the potential of the output voltage to the potential of the power voltage;
setting a detection voltage corresponding to an allow-limit degradation rate;
setting the detection voltage as the power voltage, and applying the set power voltage to the PBTI monitoring unit;
comparing a potential of the set power voltage to the potential of the output voltage that is output from the PBTI monitoring unit; and
determining whether the device is in a normal state or a defective state based on a result that is obtained by comparing the potential of the set power voltage to the potential of the output voltage.