US 12,085,410 B2
Solid-state imaging device and distance measurement device
Sozo Yokogawa, Kanagawa (JP); Yusuke Moriyama, Kanagawa (JP); Nobuhiro Kawai, Kanagawa (JP); Yuhi Yorikado, Kanagawa (JP); Fumihiko Koga, Kanagawa (JP); Yoshiki Ebiko, Kanagawa (JP); Suzunori Endo, Kanagawa (JP); and Hayato Wakabayashi, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/611,970
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Apr. 27, 2020, PCT No. PCT/JP2020/017964
§ 371(c)(1), (2) Date Nov. 17, 2021,
PCT Pub. No. WO2020/241151, PCT Pub. Date Dec. 3, 2020.
Claims priority of application No. 2019-097969 (JP), filed on May 24, 2019.
Prior Publication US 2022/0244046 A1, Aug. 4, 2022
Int. Cl. G01C 3/06 (2006.01); H04N 25/705 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01)
CPC G01C 3/06 (2013.01) [H04N 25/705 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01)] 17 Claims
OG exemplary drawing
 
1. A solid-state imaging device, comprising:
a pixel array part in which a plurality of pixels is arranged in a matrix,
wherein each of the pixels includes:
a plurality of photoelectric conversion units that each photoelectrically converts incident light to generate charges,
a floating diffusion region that accumulates charges,
a plurality of transfer circuits that transfer charges generated in each of the plurality of photoelectric conversion units to the floating diffusion region, and
a first transistor that causes a pixel signal of a voltage value corresponding to a charge amount of the charges accumulated in the floating diffusion region to appear in a signal line, wherein each of the plurality of pixels is arranged in a pixel region individually allocated on a first surface of a semiconductor substrate,
wherein the plurality of transfer circuits includes:
a plurality of first transfer circuits arranged point-symmetrically or line-symmetrically with respect to a center of the pixel region or a straight line passing through the center as an axis, and
a plurality of second transfer circuits arranged point-symmetrically or line-symmetrically with respect to the center or the straight line as an axis, wherein each of the photoelectric conversion units is provided on a one-to-one basis for a combination of a first transfer circuit and a second transfer circuit arranged in a predetermined direction in the matrix arrangement; and
a drive unit configured to drive transfer of the charge by the plurality of transfer circuits, wherein the drive unit drives the first and second transfer circuits such that transfer of the charge via the first transfer circuit is different in timing from transfer of the charge via the second transfer circuit, wherein the drive unit inputs a first drive pulse having a first phase angle with respect to a pulse of a predetermined cycle and the predetermined cycle to the first transfer circuit, and inputs a second drive pulse whose phase is shifted by 180 degrees with respect to the first drive pulse to the second transfer circuit, and wherein the drive unit drives the plurality of first transfer circuits at a same phase and drives the plurality of second transfer circuits at the same phase.