US 11,756,606 B2
Method and apparatus for recovering regular access performance in fine-grained DRAM
Sriseshan Srikanth, Austin, TX (US); Vignesh Adhinarayanan, Austin, TX (US); Jagadish B. Kotra, Austin, TX (US); and Sergey Blagodurov, Bellevue, WA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 13, 2021, as Appl. No. 17/549,359.
Prior Publication US 2023/0186976 A1, Jun. 15, 2023
Int. Cl. G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); H03K 19/17728 (2020.01); G11C 8/18 (2006.01); H03K 19/173 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/4093 (2013.01) [G11C 8/18 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01); H03K 19/1737 (2013.01); H03K 19/17728 (2013.01)] 11 Claims
OG exemplary drawing
1. A fine-grained dynamic random-access memory (DRAM) comprising:
a first memory bank including a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry;
a second memory bank; and
a dual-mode I/O circuit coupled to the I/O circuitry of each grain in the first memory bank, the dual-mode I/O circuit operating in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.