US 11,755,810 B2
Method and apparatus for performing parallel routing using a multi-threaded routing procedure
Vaughn Betz, Toronto (CA); Jordan Swartz, Toronto (CA); and Vadim Gouterman, Toronto (CA)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Altera Corporation, San Jose, CA (US)
Filed on Sep. 21, 2020, as Appl. No. 17/27,277.
Application 17/027,277 is a continuation of application No. 16/154,521, filed on Oct. 8, 2018, granted, now 10,783,310, issued on Sep. 22, 2020.
Application 16/154,521 is a continuation of application No. 15/356,791, filed on Nov. 21, 2016, granted, now 10,140,411, issued on Nov. 27, 2018.
Application 15/356,791 is a continuation of application No. 14/559,759, filed on Dec. 3, 2014, granted, now 9,536,034, issued on Jan. 3, 2017.
Application 14/559,759 is a continuation of application No. 14/245,162, filed on Apr. 4, 2014, granted, now 8,935,650, issued on Jan. 13, 2015.
Application 14/245,162 is a continuation of application No. 13/957,794, filed on Aug. 2, 2013, granted, now 8,739,105, issued on May 27, 2014.
Application 13/957,794 is a continuation of application No. 13/615,563, filed on Sep. 13, 2012, granted, now 8,533,652, issued on Sep. 10, 2013.
Application 13/615,563 is a continuation of application No. 13/311,996, filed on Dec. 6, 2011, granted, now 8,296,709, issued on Oct. 23, 2012.
Application 13/311,996 is a continuation of application No. 12/317,789, filed on Dec. 29, 2008, granted, now 8,095,906, issued on Jan. 10, 2012.
Prior Publication US 2021/0073453 A1, Mar. 11, 2021
Int. Cl. G06F 30/394 (2020.01)
CPC G06F 30/394 (2020.01) 20 Claims
OG exemplary drawing
 
1. A method, comprising:
determining a number of processors to be used to perform operations on partitions, wherein respective partitions of the partitions correspond to a respective subset of one or more cells of a plurality of cells, wherein the respective subset of the one or more cells are identified by a respective boundary box that logically separates the respective subset of one or more cells from a remaining subset of the plurality of cells, wherein the plurality of cells form a programmable logic fabric corresponding to a target programmable logic device, wherein the plurality of cells are configurable to implement a system design;
performing a first respective timing analysis on a first partition of the partitions separate from and at least partially in parallel with a second respective timing analysis of a second partition of the partitions; and
outputting results of a plurality of timing analyses and a file comprising the system design.