US 11,755,497 B2
Memory management
Andrew Brookfield Swaine, Sheffield (GB)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Mar. 10, 2021, as Appl. No. 17/197,425.
Claims priority of application No. 2004256 (GB), filed on Mar. 24, 2020.
Prior Publication US 2021/0303478 A1, Sep. 30, 2021
Int. Cl. G06F 12/1027 (2016.01)
CPC G06F 12/1027 (2013.01) [G06F 2212/45 (2013.01)] 17 Claims
OG exemplary drawing
1. A memory management apparatus comprising:
input circuitry to receive a translation request defining a first memory address within a first memory address space;
prediction circuitry to generate a predicted second memory address within a second memory address space as a predicted translation of the first memory address, the predicted second memory address being a predetermined function of the first memory address;
control circuitry to initiate processing of the predicted second memory address;
translation and permission circuitry to perform an operation to generate a translated second memory address for the first memory address associated with permission information to indicate whether memory access is permitted to the translated second memory address; and
output circuitry to provide the translated second memory address as a response to the translation request when the permission information indicates that access is permitted to the translated second memory address,
wherein the control circuitry is configured to initiate prefetching of data at the predicted second memory address before completion of the operation performed by the translation and permission circuitry for the first memory address, and
wherein the prefetch circuitry is configured to deny access to the data at the predicted second memory address responsive to the permission information indicating denial of access.