US 11,755,480 B2
Data pattern based cache management
Michael R. Seningen, Austin, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 2, 2022, as Appl. No. 17/929,544.
Application 17/929,544 is a continuation of application No. 17/033,587, filed on Sep. 25, 2020, granted, now 11,442,855.
Prior Publication US 2022/0414009 A1, Dec. 29, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
1. An apparatus, comprising:
a memory circuit with a total address space that includes a physical address space and an extended address space, wherein the physical address space includes a pattern address space, and wherein addresses included in the pattern address space correspond to locations where a background data pattern is stored; and
a control circuit configured to:
receive a first read access request including a first read address; and
in response to a determination that the first read address is included in the pattern address space, return the background data pattern while holding the memory circuit in an inactive state.