US 11,755,407 B2
Multi-rate ECC parity for fast SLC read
Dudy David Avraham, Even Yehuda (IL); Ran Zamir, Ramat Gan (IL); and Eran Sharon, Rishon Lezion (IL)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on May 26, 2021, as Appl. No. 17/331,346.
Prior Publication US 2022/0385303 A1, Dec. 1, 2022
Int. Cl. G06F 11/10 (2006.01); H03M 13/09 (2006.01); H03M 13/11 (2006.01)
CPC G06F 11/1068 (2013.01) [H03M 13/098 (2013.01); H03M 13/1105 (2013.01); H03M 13/118 (2013.01)] 10 Claims
OG exemplary drawing
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
create a dual parity construction matrix, wherein the dual parity construction matrix comprises:
a full parity form that includes a payload, a first parity portion, and a second parity portion, wherein the full parity form includes the payload arranged in a first half and a second half, wherein the first half comprises half of the payload, wherein the second half comprises another half of the payload, and wherein the first half and the second half are disjointed; and
a reduced parity form that includes the payload and the first parity portion, wherein the second parity portion is 0;
receive a read request for data associated with the dual parity construction matrix;
determine that the read request is a single level cell (SLC) read request; and
transfer and decode the data using reduced parity.