US 11,755,333 B2
Coprocessor prefetcher
Brandon H. Dwiel, Boston, MA (US); Andrew J. Beaumont-Smith, Cambridge, MA (US); Eric J. Furbish, Austin, TX (US); John D. Pape, Cedar Park, TX (US); Stephen G. Meier, Los Altos, CA (US); and Tyler J. Huberty, Sunnyvale, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Dec. 10, 2021, as Appl. No. 17/643,765.
Claims priority of provisional application 63/247,703, filed on Sep. 23, 2021.
Prior Publication US 2023/0092898 A1, Mar. 23, 2023
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3881 (2013.01) [G06F 9/382 (2013.01); G06F 9/383 (2013.01); G06F 9/3877 (2013.01)] 20 Claims
OG exemplary drawing
1. An apparatus comprising:
a processor configured to execute processor instructions;
a coprocessor configured to execute coprocessor instructions, wherein the processor instructions and the coprocessor instructions appear together in code sequences fetched by the processor, wherein the processor is configured to provide the coprocessor instructions to the coprocessor; and
a coprocessor prefetcher configured to:
monitor a code sequence fetched by the processor;
in response to identifying a presence of the coprocessor instructions in the code sequence, capture memory addresses, generated by the processor, of operand data for the coprocessor instructions; and
issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.