US 11,755,331 B2
Writeback hazard elimination using a plurality of temporary result-storage elements
Skanda K Srinivasa, Austin, TX (US); and Christopher S Thomas, Austin, TX (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by APPLE INC., Cupertino, CA (US)
Filed on Jul. 11, 2021, as Appl. No. 17/372,465.
Prior Publication US 2023/0011446 A1, Jan. 12, 2023
Int. Cl. G06F 9/38 (2018.01); G06F 1/10 (2006.01)
CPC G06F 9/3867 (2013.01) [G06F 1/10 (2013.01); G06F 9/3826 (2013.01); G06F 9/3857 (2013.01)] 15 Claims
OG exemplary drawing
1. A processor, comprising:
a processing pipeline, configured to process program operations and to write, to a result storage, up to a predefined maximal number of results of the processed program operations per clock cycle;
a plurality of result-storage elements, configured to store respective ones of the results; and
writeback circuitry, configured to:
detect a writeback conflict event in which the processing pipeline produces simultaneous results that exceed the predefined maximal number of results, for writing to the result storage in a same clock cycle;
in response to detecting the writeback conflict event,
temporarily store at least a given result, from among the simultaneous results, in a given result-storage element, and
subsequently write the temporarily-stored given result from the given result-storage element to the result storage,
wherein the writeback circuitry is further configured to:
identify an operation that is processed in the processing pipeline and requires an input that is available in the result-storage elements;
predict a beginning and an end of a range of clock cycles during which the input will be available in the result-storage elements;
determine a time at which the operation will require the input; and
if the time falls within the predicted range of clock cycles, provide the input to the operation from the result-storage elements.