US 11,755,240 B1
Concurrent multi-bit subtraction in associative memory
Moshe Lazer, Binyamina (IL); and Eyal Amiel, Rosh HaAyin (IL)
Assigned to GSI Technology Inc., Sunnyvale, CA (US)
Filed by GSI Technology Inc., Sunnyvale, CA (US)
Filed on Feb. 23, 2022, as Appl. No. 17/678,073.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 8 Claims
OG exemplary drawing
1. A method for an associative memory device, the method comprising:
storing a plurality of pairs of multi-bit operands X and Y in rows of a memory array of said associative memory device, each pair in a different column of said memory array;
cells in a column connected by a first bit-line providing a value of activated cells and a second bit-line providing an inverse value of said activated cells, bits of X in first rows and bits of Y in second rows;
reading an inverse value of a bit stored in each of said second rows using said second bit-line and writing said inverse value to third rows; and
concurrently, on all columns, performing multi-bit add operations between a value of X, an inverse value of Y and a carry-in bit initiated to 1, thereby providing a difference between X and Y in each of said columns.