US 12,414,470 B2
Semiconductor component including a dielectric layer
Daniel Monteiro Diniz Reis, Esslingen Am Neckar (DE); Daniel Pantel, Mundelsheim (DE); Frank Schatz, Kornwestheim (DE); Jochen Tomaschko, Gaeufelden (DE); Mathias Mews, Reutlingen (DE); and Timo Schary, Aichtal-Neuenhaus (DE)
Assigned to ROBERT BOSCH GMBH, Stuttgart (DE)
Appl. No. 17/614,706
Filed by Robert Bosch GmbH, Stuttgart (DE)
PCT Filed Jun. 23, 2020, PCT No. PCT/EP2020/067568
§ 371(c)(1), (2) Date Nov. 29, 2021,
PCT Pub. No. WO2021/004782, PCT Pub. Date Jan. 14, 2021.
Claims priority of application No. 10 2019 209 964.5 (DE), filed on Jul. 5, 2019; application No. 10 2019 209 965.3 (DE), filed on Jul. 5, 2019; application No. 10 2019 210 032.5 (DE), filed on Jul. 8, 2019; and application No. 10 2019 210 033.3 (DE), filed on Jul. 8, 2019.
Prior Publication US 2022/0238791 A1, Jul. 28, 2022
Int. Cl. H10N 30/20 (2023.01); H10N 30/00 (2023.01); H10N 30/076 (2023.01); H10N 30/853 (2023.01); H10N 30/87 (2023.01)
CPC H10N 30/2047 (2023.02) [H10N 30/076 (2023.02); H10N 30/704 (2024.05); H10N 30/8554 (2023.02); H10N 30/87 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A semiconductor component, comprising:
at least one dielectric layer; and
at least one first electrode and at least one second electrode,
wherein at least one first defect type and at least one second defect type, which is different from the first defect type, are present in the dielectric layer, the at least one first defect type and the at least one second defect type accumulating at one of the first and second electrodes, as a function of a main operating voltage applied between the first electrode and the second electrode, and a main operating temperature that is present at characteristic times τ1 and τ2, and generating maximum changes in barrier height δΦ1 and δΦ2 at the first and second electrodes, τ1 and δΦ1 being associated with the first defect type, and τ2 and δΦ2 being associated with the second defect type, where τ1<τ2 and δΦ1<δΦ2 apply.