US 12,414,400 B2
High performance image sensor
Tung-Ting Wu, Taipei (TW); Jhy-Jyi Sze, Hsin-Chu (TW); and Yimin Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 12, 2024, as Appl. No. 18/741,029.
Application 18/741,029 is a continuation of application No. 18/304,521, filed on Apr. 21, 2023, granted, now 12,100,726.
Application 18/304,521 is a continuation of application No. 17/236,343, filed on Apr. 21, 2021, granted, now 11,670,663, issued on Jun. 6, 2023.
Application 17/236,343 is a continuation of application No. 16/352,164, filed on Mar. 13, 2019, granted, now 10,991,746, issued on Apr. 27, 2021.
Claims priority of provisional application 62/751,761, filed on Oct. 29, 2018.
Prior Publication US 2024/0332338 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/146 (2006.01); H01L 31/036 (2006.01); H10F 39/00 (2025.01); H10F 39/18 (2025.01); H10F 77/16 (2025.01)
CPC H10F 39/811 (2025.01) [H10F 39/014 (2025.01); H10F 39/18 (2025.01); H10F 39/8027 (2025.01); H10F 77/16 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated chip, comprising:
forming a masking layer on a first side of a substrate;
performing a first etching process on the first side of the substrate with the masking layer in place;
removing the masking layer; and
performing a second etching process on the first side of the substrate after removing the masking layer, wherein the first etching process and the second etching process collectively form a plurality of topographical features respectively having a triangular shape in a cross-section.