| CPC H10D 87/00 (2025.01) [H01L 21/76283 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53228 (2013.01)] | 20 Claims |

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1. A method for forming an integrated chip (IC), the method comprising:
receiving a workpiece, wherein the workpiece comprises a semiconductor device over a device substrate and comprises an interlayer dielectric (ILD) structure over the semiconductor device and over a first side of the device substrate, wherein the device substrate is a semiconductor material;
forming a device layer by performing a thinning process on a second side of the device substrate that reduces a thickness of the device substrate, wherein the second side of the device substrate is opposite the first side of the device substrate;
after the thinning process, forming an insulating layer on a side of the device layer, wherein the side of the device layer is opposite the ILD structure; and
forming a metal layer on the insulating layer, such that the insulating layer vertically separates the metal layer from the device layer;
forming a dielectric layer on the metal layer, such that the metal layer vertically separates the dielectric layer from the insulating layer;
forming a first opening that extends vertically through the dielectric layer and vertically through the metal layer, wherein the first opening exposes a portion of the insulating layer;
forming a first isolation structure in the first opening by filling the opening with a dielectric material;
forming a second opening that extends vertically through the first isolation structure, the portion of the insulating layer, the device layer, and the ILD structure; and
forming a first through-substrate via (TSV) in the second opening.
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