US 12,414,372 B2
Display device and tiled display device including the same
Dong Hee Shin, Asan-si (KR); Sun Kwun Son, Suwon-si (KR); and Na Hyeon Cha, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on Nov. 2, 2021, as Appl. No. 17/517,623.
Claims priority of application No. 10-2021-0033898 (KR), filed on Mar. 16, 2021.
Prior Publication US 2022/0302175 A1, Sep. 22, 2022
Int. Cl. G09G 3/32 (2016.01); H01L 25/16 (2023.01); H01L 27/12 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H10D 86/60 (2025.01) [G09G 3/32 (2013.01); H01L 25/167 (2013.01); H10D 86/441 (2025.01); G09G 2300/026 (2013.01); G09G 2300/0413 (2013.01); G09G 2300/0421 (2013.01); G09G 2310/0205 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/08 (2013.01); H01L 24/32 (2013.01); H01L 25/0655 (2013.01); H01L 25/162 (2013.01); H01L 2224/32137 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display device comprising:
a display panel including a display area and a non-display area, wherein the display area includes scan lines, data lines, and pixels electrically connected to the scan lines and the data lines, wherein the non-display area abuts the display area and includes data connection lines, and wherein the data connection lines are respectively electrically connected to the data lines; and
a scan driving unit including scan stages and auxiliary stages, wherein the scan stages are disposed on the display area and the non-display area and are electrically connected to the scan lines for providing scan signals through the scan lines to the pixels, wherein the auxiliary stages are disposed on the non-display area, include auxiliary transistors, and are for providing carry signals to one or more of the scan stages,
wherein at least one stage of the scan stages is disposed in the non-display area and not in the display area,
remaining stages of the scan stages are disposed in the display area and not in the non-display area,
each of the stages receives a start signal or an input carry signal,
each of the stages outputs a carry signal and a scan signal,
each of the scan stages includes a first scan transistor, a clock terminal, a first node, and a first scan capacitor, wherein the clock terminal receives a first clock signal, wherein the first scan transistor outputs the first clock signal to one of the scan lines in accordance with a voltage of a first node, and wherein the first scan capacitor is disposed between a gate electrode of the first scan transistor and a source electrode of the first scan transistor,
the first scan transistor of a first scan stage among the scan stages is disposed between two adjacent pixels in a first direction, and wherein the first scan capacitor of the first scan stage is disposed between other two adjacent pixels in the first direction, and
the first scan transistor of the first scan stage is aligned with the first scan capacitor of the second scan stage in a second direction different from the first direction.