US 12,414,367 B2
Tapered device for lateral gate all around devices
Lars Liebmann, Mechanicville, NY (US); Jeffrey Smith, Clifton Park, NY (US); Daniel Chanemougame, Niskayuna, NY (US); and Paul Gutwin, Williston, VT (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Aug. 5, 2022, as Appl. No. 17/882,229.
Claims priority of provisional application 63/244,287, filed on Sep. 15, 2021.
Prior Publication US 2023/0078381 A1, Mar. 16, 2023
Int. Cl. H10D 84/85 (2025.01); H10D 88/00 (2025.01); H10D 89/10 (2025.01)
CPC H10D 84/856 (2025.01) [H10D 88/01 (2025.01); H10D 89/10 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a lower channel structure;
an upper channel structure formed vertically over the lower channel structure;
a first transistor device including a lower gate formed around a first portion of the lower channel structure, an upper gate formed around a first portion of the upper channel structure, and a separation layer formed between and separating the upper gate and the lower gate; and
a second transistor device including a common gate formed around a second portion of the lower channel structure and a second portion of the upper channel structure,
wherein the first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, the second portion of the lower channel structure is equal to the second portion of the upper channel structure in width, and the first portion of the lower channel structure has a first width less than a second width of the second portion of the lower channel structure.