US 12,414,366 B2
Co-integration of high voltage (HV) and low voltage (LV) transistor structures, using channel height and spacing modulation
Prashant Majhi, San Jose, CA (US); Anand Murthy, Portland, OR (US); Glenn Glass, Portland, OR (US); Rushabh Shah, Hillsboro, OR (US); and Susmita Ghose, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2021, as Appl. No. 17/557,517.
Prior Publication US 2023/0197724 A1, Jun. 22, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/856 (2025.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure comprising:
a first non-planar semiconductor device comprising
a first plurality of bodies comprising a semiconductor material,
a first gate structure at least in part wrapped around the first plurality of bodies, the first gate structure including (i) a first gate electrode and (ii) a first gate dielectric between the first plurality of bodies and the first gate electrode, and
a first source region and a first drain region, each of the first plurality of bodies having a length that extends laterally between the first source region and the first drain region;
a second non-planar semiconductor device comprising
a second plurality of bodies comprising a semiconductor material,
a second gate structure at least in part wrapped around the second plurality of bodies, the second gate structure including (i) a second gate electrode and (ii) a second gate dielectric between the second plurality of bodies and the second gate electrode, and
a second source region and a second drain region, each of the second plurality of bodies having a length that extends laterally between the second source region and the second drain region,
wherein a first height of a first body of the first plurality of bodies is at least 5% different from a second height of a second body of the second plurality of bodies, wherein the first height is measured under the first gate structure and in a vertical direction that is perpendicular to the length of the first body, and the second height is measured under the second gate structure and in a vertical direction that is perpendicular to the length of the second body,
wherein each body of the first and second plurality of bodies includes corresponding tip regions and a corresponding middle region between the corresponding tip regions, and
wherein a first vertical spacing between corresponding tip regions of two adjacent bodies of the first plurality of bodies is within 5% of a second vertical spacing between corresponding tip regions of two adjacent bodies of the second plurality of bodies.