| CPC H10D 84/834 (2025.01) [H10B 10/12 (2023.02); H10D 1/00 (2025.01); H10D 30/6213 (2025.01); H10D 64/017 (2025.01); H10D 64/517 (2025.01); H10D 64/518 (2025.01); H10D 64/667 (2025.01); H10D 84/014 (2025.01); H10D 84/0142 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01)] | 11 Claims |
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1. A semiconductor device, comprising:
a substrate including a first active region, a second active region, and a first field insulating layer between the first active region and the second active regions, the first field insulating layer directly contacting the first active region and the second active regions; and
a first gate structure on the substrate, the first gate structure crossing the first active region, the second active region, and the first field insulating layer,
wherein the first gate structure includes a first p-type gate electrode and a first n-type gate electrode directly contacting each other,
wherein the first p-type gate electrode includes a first work function layer on the first active region and the first field insulating layer, and a first upper conductive layer on the first work function layer,
wherein the first n-type gate electrode includes a second work function layer on the second active region and the first field insulating layer, and a second upper conductive layer on the second work function layer,
wherein the first work function layer and the second work function layer are in direct contact with each other and are formed of the same material layer,
wherein a thickness of the first work function layer is different from a thickness of the second work function layer, and
wherein an overlapping width of the first p-type gate electrode and the first field insulating layer is different from an overlapping width of the first n-type gate electrode and the first field insulating layer.
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