US 12,414,362 B2
Fins disposed on stacks of nanostructures where the nanostructures are wrapped around by a gate
Li-Zhen Yu, New Taipei (TW); Huan-Chieh Su, Changhua County (TW); Lin-Yu Huang, Hsinchu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 27, 2022, as Appl. No. 17/849,725.
Prior Publication US 2023/0420455 A1, Dec. 28, 2023
Int. Cl. H10D 84/83 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/83 (2025.01) [H01L 21/02603 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of stacks, each stack comprising a plurality of nanostructures stacked over each other;
a gate structure, wrapping around the nanostructures and extending between the stacks;
source and drain structures; and
a plurality of fin structures, disposed on the stacks respectively, wherein a first surface of the gate structure between the stacks is between the nanostructures and first surfaces of the fin structures facing the nanostructures.