| CPC H10D 84/811 (2025.01) [H01L 21/76224 (2013.01); H10B 41/49 (2023.02); H10D 1/68 (2025.01); H10D 1/692 (2025.01); H10D 1/696 (2025.01); H10D 1/711 (2025.01); H10D 1/714 (2025.01); H10D 1/716 (2025.01); H10D 84/0135 (2025.01); H10D 84/038 (2025.01)] | 22 Claims |

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1. An integrated circuit including a capacitive element, comprising:
a first conductive layer disposed on a front face of a substrate, delimited by an outline, and forming a first part of a first electrode of the capacitive element;
a low voltage dielectric layer covering the first conductive layer;
a second conductive layer on the low voltage dielectric layer and including:
a first portion located over an upper surface of the first conductive layer at a central zone of the first conductive layer and forming a second electrode of the capacitive element;
a second portion comprising an inner border part located over the upper surface of the first conductive layer and surrounding the first portion and an outer border part located over the front face of the substrate and surrounding the first conductive layer;
the second portion forming a second part of the first electrode of the capacitive element;
wherein the first portion and the second portion of the second conductive layer are electrically separated; and
wherein the first conductive layer is electrically connected to the second portion of the second conductive layer.
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