US 12,414,356 B2
Gate structure and method of forming same
Shahaji B. More, Hsinchu (TW); Chandrashekhar Prakash Savant, Hsinchu (TW); and Chun Hsiung Tsai, Xinpu Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/366,871.
Application 17/811,651 is a division of application No. 16/564,243, filed on Sep. 9, 2019, granted, now 11,404,327, issued on Aug. 2, 2022.
Application 18/366,871 is a continuation of application No. 17/811,651, filed on Jul. 11, 2022, granted, now 11,837,507.
Prior Publication US 2023/0377995 A1, Nov. 23, 2023
Int. Cl. H10D 84/03 (2025.01); H01L 21/28 (2025.01); H01L 21/3213 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/28088 (2013.01); H01L 21/32134 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 64/017 (2025.01); H10D 64/667 (2025.01); H10D 84/0179 (2025.01); H10D 84/0193 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a gate stack over an active region of a substrate, the gate stack comprising:
a gate dielectric layer over the active region;
a P-type work function layer on the gate dielectric layer;
an N-type work function layer over the P-type work function layer;
a first protective layer over the N-type work function layer;
a second protective layer over the first protective layer, an upper portion of the N-type work function layer being in physical contact with an upper portion of the second protective layer; and
a conductive material over the second protective layer.