| CPC H10D 84/038 (2025.01) [H10D 30/6219 (2025.01); H10D 62/151 (2025.01); H10D 84/017 (2025.01); H10D 84/0184 (2025.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/853 (2025.01)] | 20 Claims |
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1. A method for manufacturing a semiconductor device, comprising:
forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate;
forming a first gate structure and a second gate structure respectively over a first region of the first semiconductor fin and a first region of the second semiconductor fin;
forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin;
etching a first source/drain recess in the second region of the first semiconductor fin;
forming an n-type source/drain epitaxial structure in the first source/drain recess and in direct contact with the first dummy spacer;
forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer;
etching a second source/drain recess in the second region of the second semiconductor fin; and
forming a p-type source/drain epitaxial structure in the second source/drain recess.
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