US 12,414,345 B2
Manufacturing method of semiconductor device and semiconductor wafer
Hitoshi Fujioka, Nisshin (JP); Takeshi Koshiba, Nisshin (JP); Norihiro Togawa, Nisshin (JP); and Takuji Arauchi, Nisshin (JP)
Assigned to DENSO CORPORATION, Kariya (JP); TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP); and MIRISE Technologies Corporation, Nisshin (JP)
Filed by DENSO CORPORATION, Kariya (JP); TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP); and MIRISE Technologies Corporation, Nisshin (JP)
Filed on Feb. 2, 2023, as Appl. No. 18/163,423.
Claims priority of application No. 2022-035666 (JP), filed on Mar. 8, 2022.
Prior Publication US 2023/0290833 A1, Sep. 14, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 23/544 (2006.01); H10D 12/01 (2025.01); H10D 62/832 (2025.01)
CPC H10D 62/8325 (2025.01) [H01L 23/544 (2013.01); H10D 12/031 (2025.01); H01L 2223/54426 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor device, comprising:
preparing a silicon carbide substrate that has an upper surface on which an alignment mark having a recessed shape is disposed, a perpendicular line that is perpendicular to the upper surface of the silicon carbide substrate being inclined with respect to a [0001] direction toward a [11-20] direction;
growing an epitaxial layer on the upper surface of the silicon carbide substrate so as to cover the alignment mark; and
forming a structure on or above the upper surface of the silicon carbide substrate, wherein
the structure is formed at a position apart from the alignment mark by an interval P in the [11-20] direction along the upper surface of the silicon carbide substrate, and
the interval P satisfies a relationship of D/tan θ<P<10D/tan θ, where D is a depth of the alignment mark and θ is an inclination angle of the perpendicular line with respect to the [0001] direction.