US 12,414,335 B2
Semiconductor device comprising conductive layers functioning as first and second gate electrodes of a transistor
Shunpei Yamazaki, Setagaya (JP); Daisuke Matsubayashi, Atsugi (JP); and Keisuke Murayama, Chigasaki (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Mar. 5, 2024, as Appl. No. 18/595,629.
Application 18/595,629 is a continuation of application No. 17/500,020, filed on Oct. 13, 2021, granted, now 11,929,437.
Application 17/500,020 is a continuation of application No. 17/065,635, filed on Oct. 8, 2020, granted, now 11,355,645, issued on Jun. 4, 2022.
Application 17/065,635 is a continuation of application No. 16/707,432, filed on Dec. 9, 2019, granted, now 10,872,981, issued on Dec. 22, 2020.
Application 16/707,432 is a continuation of application No. 16/180,210, filed on Nov. 5, 2018, granted, now 10,559,699, issued on Feb. 11, 2020.
Application 16/180,210 is a continuation of application No. 15/262,547, filed on Sep. 12, 2016, granted, now 10,158,026, issued on Dec. 18, 2018.
Application 15/262,547 is a continuation of application No. 14/594,991, filed on Jan. 12, 2015, granted, now 9,472,679, issued on Oct. 18, 2016.
Application 14/594,991 is a continuation of application No. 13/860,792, filed on Apr. 11, 2013, granted, now 8,946,702, issued on Feb. 3, 2015.
Claims priority of application No. 2012-091539 (JP), filed on Apr. 13, 2012.
Prior Publication US 2024/0250181 A1, Jul. 25, 2024
Int. Cl. H10D 30/67 (2025.01); H10D 30/60 (2025.01)
CPC H10D 30/6755 (2025.01) [H10D 30/611 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor;
a second transistor; and
a capacitor,
wherein the first transistor comprises a first channel formation region including silicon,
wherein the second transistor comprises a second channel formation region,
wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one electrode of the capacitor,
wherein a first insulating layer is provided over the first channel formation region,
wherein a first conductive layer in contact with a top surface of the first insulating layer comprises a region configured to function as the gate electrode of the first transistor,
wherein a second insulating layer is provided over the first conductive layer,
wherein a second conductive layer in contact with a top surface of the second insulating layer is configured to function as a first gate electrode of the second transistor,
wherein a third insulating layer is provided in contact with a top surface of the second conductive layer,
wherein a fourth insulating layer is provided in contact with a top surface of the third insulating layer,
wherein an oxide semiconductor layer in contact with a top surface of the fourth insulating layer comprises the second channel formation region,
wherein a fifth insulating layer is provided over the oxide semiconductor layer,
wherein a third conductive layer in contact with a top surface of the fifth insulating layer is configured to function as a second gate electrode of the second transistor,
wherein a fourth conductive layer in contact with a top surface of the oxide semiconductor layer comprises a region configured to function as the one of the source electrode and the drain electrode of the second transistor,
wherein a fifth conductive layer in contact with the top surface of the oxide semiconductor layer comprises a region configured to function as the other of the source electrode and the drain electrode of the second transistor,
wherein a sixth conductive layer in contact with the top surface of the fifth insulating layer overlaps with the fourth conductive layer,
wherein a seventh conductive layer provided over the sixth conductive layer is electrically connected to the fifth conductive layer,
wherein an eighth conductive layer in contact with the top surface of the second insulating layer overlaps with the fourth conductive layer,
wherein the seventh conductive layer comprises a region overlapping the second channel formation region and a region overlapping the capacitor,
wherein the second conductive layer and the eighth conductive layer comprise a same material, and
wherein the third conductive layer and the sixth conductive layer comprise a same material.