US 12,414,331 B2
Isolation for multigate devices
Ko-Cheng Liu, Hsinchu (TW); Chang-Miao Liu, Hsinchu (TW); and Ming-Lung Cheng, Kaohsiung County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 6, 2022, as Appl. No. 17/833,322.
Claims priority of provisional application 63/311,087, filed on Feb. 17, 2022.
Prior Publication US 2023/0261077 A1, Aug. 17, 2023
Int. Cl. H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 62/121 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01)] 20 Claims
OG exemplary drawing
 
9. A device comprising:
a first epitaxial source/drain and a second epitaxial source/drain disposed over a substrate, wherein an elevated portion of the substrate is between the first epitaxial source/drain and the second epitaxial source/drain;
an insulation layer disposed over the elevated portion of the substrate and between the first epitaxial source/drain and the second epitaxial source/drain;
a channel layer disposed over the elevated portion of the substrate and between the first epitaxial source/drain and the second epitaxial source/drain;
an isolation feature disposed over the substrate, wherein the elevated portion of the substrate extends through the isolation feature; and
a gate disposed over the elevated portion of the substrate and between the first epitaxial source/drain and the second epitaxial source/drain, wherein:
the gate wraps around the channel layer,
the gate includes a gate dielectric and a gate electrode,
the insulation layer is between a first portion of the gate and the elevated portion of the substrate and between a second portion of the gate and the isolation feature, and
a bottom surface of the second portion of the gate is above a top surface of the elevated portion of the substrate.