US 12,414,328 B2
Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors
Huimei Zhou, Albany, NY (US); Julien Frougier, Albany, NY (US); Nicolas Loubet, Guilderland, NY (US); Ruilong Xie, Niskayuna, NY (US); Miaomiao Wang, Albany, NY (US); and Veeraraghavan S. Basker, Schenectady, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 13, 2021, as Appl. No. 17/548,751.
Prior Publication US 2023/0187514 A1, Jun. 15, 2023
Int. Cl. H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 62/118 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01)] 7 Claims
OG exemplary drawing
 
1. A method for co-integrating a gate-all-around (GAA) nanosheet device with a comb-nanosheet device, the method comprising:
forming a GAA nanosheet device in a first region of a substrate, the GAA nanosheet device comprising a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack; and
forming a comb-nanosheet device in a second region of a substrate, the comb-nanosheet device comprising a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack, wherein the second fin spacing distance is less than the first fin spacing distance;
wherein forming the comb-nanosheet device comprises forming a shallow trench isolation (STI) liner and forming a dielectric pillar, wherein the STI liner and the dielectric pillar comprise portions of a monolithic structure;
wherein forming the comb-nanosheet device further comprises forming a first source or drain region having a first doping type and forming a second source or drain region having the first doping type; and
wherein the dielectric pillar is recessed such that the first source or drain region and the second source or drain region merge.