US 12,414,327 B2
Lateral confinement of source drain epitaxial growth in non-planar transistor for cell height scaling
Nitesh Kumar, Beaverton, OR (US); Mohammed Hasan, Aloha, OR (US); Vivek Thirtha, Portland, OR (US); Nikhil Mehta, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/359,440.
Prior Publication US 2022/0416044 A1, Dec. 29, 2022
Int. Cl. H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 84/85 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 84/85 (2025.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a plurality of nanowires above a sub-fin;
a gate stack over the plurality of nanowires and the sub-fin; and
epitaxial source or drain structures on opposite ends of the plurality of nanowires, the epitaxial source or drain structures having substantially vertical opposing sidewalls extending a height of the plurality of nanowires, and a substantially lateral wingspan that is symmetric around the plurality of nanowires such that a first distance from a left edge of the plurality of nanowires to a left edge of the epitaxial source or drain structures is substantially equal as a second distance from a right edge of the plurality of nanowires to a right edge of the epitaxial source or drain structures.